Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 45 nanometers with smaller geometries on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools, and methodologies in all aspects of digital chip design and manufacturing. The widespread use of Test Synthesis coupled with powerful pre-silicon verification approaches is one factor that has enabled test to keep up with the increasing chip complexity.

This year ITSW moves to a new location at the University of Texas, Austin. This year’s workshop will look at all aspects of test synthesis such as system bringup, system debug tools and architectures, re-use of pre-silicon DFT structures for post-silicon testing, hand-off of test IP, defect modeling, system test coverage metrics, SiP testing, system-level diagnostic methods, emerging standards for embedded testing, No Trouble Found methods, dealing with variations and imperfections inherent in the manufacturing process etc. As always ITSW will consider papers in any area of Test Synthesis including, but not limited to:

To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format, to the Program Chair by January 7, 2009. Acceptance notifications will be sent out on February 9, 2009. Please include the names, affiliations, and full contact information of all authors. Also, indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no formal proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop.