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Fri, 03/06/2009 - 12:49 — sislab

Source: http://www.tttc-vts.org/public_html/new/2009/index.php

The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, and verification / validation of microelectronic circuits and systems.
The VTS Program Committee invites original, unpublished paper submissions for VTS 2009. Paper submissions should be complete manuscripts, up to six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status.

Major topics include, but are not limited to:

  • Analog, M-S & RF Test
  • Automatic Test Generation
  • ATE Architecture & SW
  • Board & System Test
  • Built-In Self-Test (BIST)
  • Current Based Test
  • Defect Tolerance
  • Delay & Performance Test
  • Design for Testability (DFT)
  • Design Verification/Validation
  • Diagnosis and Debug
  • Embedded System Test
  • Embedded Test Methods
  • FPGA Test
  • Fault Modeling and Simulation
  • Infrastructure IP
  • Memory Test and Repair
  • Microprocessor Test
  • 3D System Test
  • Nanometer Technologies Test
  • On-Line Test
  • Power Issues in Test
  • Self-Repair & Fault Tolerance
  • Sensor, MEMS, Microsystem Test
  • SOC and SiP Test
  • Standards
  • Test Resource Partitioning
  • Test Economics
  • Thermal Test
  • Test Data Compression
  • Test of Biomedical Devices
  • Test of High-Speed I/O
  • Test Quality and Reliability
  • Yield Analysis & Optimization
    • Undefined
    Vietnamese dynamic contents: 
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    IEEE VLSI Test Symposium (VTS 2009), California, USA

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    VNU University of Engineering and Technology (VNU-UET),
    Vietnam National University, Hanoi (VNU)
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