Organizers:

- José Flich, Techn. University of Valencia, Spain (General Co-Chair)
- Davide Bertozzi, University of Ferrara, Italy (General Co-Chair)
- Tor Skeie, Simula Research Labs, Norway (Program Co-Chair)
- Marcello Lajolo, NEC Laboratories America, USA (Program Co-Chair)
- Daniele Ludovici, TUDelft, The Netherlands (Publicity Chair)
- José Duato, Techn. University of Valencia, Spain (Steering Committee)
- Manolis Katevenis, FORTH-ICS, Greece (Steering Committee)

Embedded and other computation systems no longer operate in isolation,
but are interconnected in various ways. While bus-based or wireless
communication can be used in low-throughput applications, mainstream
trends for high-performance designs turn to switch-based
interconnections using point-to-point links.

This workshop concerns interconnection network architectures,
whether on-chip or multi-chip.
Topics of interest, within the context of interconnection networks,
include but are not limited to:

   * Networks-on-Chip (NoC)
   * Multi-Chip Interconn. Networks, including Cluster Interconnects
   * "Commodity Switches" as general-purpose building blocks
   * Switching, buffering, and routing architectures
   * Flow control and congestion management in switching fabrics
   * Virtualization
   * Topology exploration
   * Timing, synchronous/asynchronous communication
   * Reliability, availability, fault tolerance
   * Area/power versus functionality/QoS support in NoC architectures
   * Design space exploration
   * NoC physical link design
   * NoC testing and verification

The goal of the workshop is to provide a forum for presenting and
discussing mostly work in progress, or ideas for future research in
response to future trends.
Submissions from EU projects in progress as well as seminal work and new
ideas to stimulate advances in the field are specifically encouraged.
Work-in-progress papers with few experimental results are welcome, as
long as they have been carefully thought out and are intuitively sound
and implementable.

This is the fourth year of the workshop. In the previous editions the
workshop exhibited a competent audience and interesting discussions
arose from the different presentations of authors and from the keynote.

Important dates:

Submission deadline: November 20th, 2009
Notification to authors: December 18th, 2009
Workshop: January 24th, 2010

Program committee:

- Olav Lysne, Simula Research Labs (Norway)
- Ulrich Brüning, Univ. Heidelberg (Germany)
- Marcello Coppola, STMicroelectronics (France)
- Ran Ginosar, Technion (Israel)
- Janusz Kleban, Poznan Univ. of Technology (Poland)
- Cyriel Minkenberg, IBM (Zurich)
- Robert Mullins, Univ. Cambridge (UK)
- José Luis Sánchez, UCLM (Spain)
- Li Shiuan Peh - MIT (USA)
- Pascal Vivet - CEA-LETI (France)
- Pedro Javier García - University of Castilla-La Mancha (Spain)
- Sudhakar Yalamanchili - Georgia Institute of Technology (USA)
- Partha Kundu - INTEL (USA)
- Maurizio Palesi - University of Catania (Italy)
- Giorgos Dimitrakopoulos - Univ. of West Macedonia, Kozani (Greece)
- José Angel Gregorio - Univ. of Cantabria (Spain)
- Dionisios Pnevmatikatos - ICS-FORTH (Greece)
- Kees Goessens - NXP and TU Delft (The Netherlands)
- Dimitris Lioupis - University of Patras (Greece)

Paper submission:

The submission procedure will be through the EasyChair web-page
(http://www.easychair.org/conferences/?conf=inaocmc10).
Papers must be in PDF format and should include title,
authors and affiliation, e-mail address of the contact author.
Submissions must be limited to 4 pages (two columns, 10pt).
Papers deviating significantly from these paper size and formatting
rules may be rejected without review