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The Asian Test Symposium (ATS) provides an international forum for engineers and researchers from all countries of the world, especially from Asia, to present and discuss various aspects of device, board and system testing with design, manufacturing and field considerations in mind. The official language of the symposium is English. Topics of interest include, but are not limited to:
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| Key Dates | |
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Early Registration Due Date: Oct. 24th, 2008 |
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| The Venue | |
| Keio Plaza Hotel Sapporo 2-1 North5 West7,Chuou-ku,Sapporo,Hokkaido,Japan tel : +81-11-271-0111fax : +81-11-271-794 |
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| Registration | |
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Please fill out a registration form and E-MAIL or FAX or Mail to ATS'08 Registration Chair. Prof. Toshinori Hosokawa (ATS’08 Registration Chair) To download Registration Forms, click here for PDF, and here for Word. |
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| Advance Program | |
Nov 24th, 20089:00-12:00 Tutorial 1 13:30- 16:30 Tutorial 2 Nov 25th, 20089:00-10:10 Plenary Session 19:00-9:20 Opening Remarks 9:20-9:45 Keynote Speech 1 9:45-10:10 Keynote Speech 2 10:40-12:00 Plenary Session 210:40-11:20 Invited Talk 1 11:20-12:00 Invited Talk 2 13:00-14:15 Session 3A: Test Data & Response CompressionNot All Xs are Bad for Scan Compression Evaluation of Entropy Driven Compression Bounds on Industrial Designs 13:00-14:15 Session 3B: Test Generation and Fault SimulationUntestable Fault Identification in Sequential Circuits Using Model-Checking A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint LIFTING: a Flexible Open-Source Fault Simulator 13:00-14:15 Session 3C: RF TestingDigitally-Assisted Analog/RF Testing for Mixed-Signal SoCs Low-Cost One-Port Approach for Testing Integrated RF Substrates Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems 15:15-16:30 Session 4A: Test Compression and BISTInterconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself 15:15-16:30 Session 4B: Test Generation for Physical FaultsXPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults A Multi-Valued Algebra for Capacitance Induced Crosstalk Delay Faults Increasing Defect Coverage by Generating Test Vectors for Stuck-open Faults 15:15-16:30 Session 4C: Analog and Mixed-Signal TestTechnique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity A Reduced Code Linearity Test Method for Pipelined A/D Converters Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry Nov 26th, 20089:00-10:15 Session 5A: Delay TestingIdentifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay 9:00-10:15 Session 5B: Special Session: Analog Production Test 1Effects of Advances in Analog, Mixed Signal and IO circuits on Test Strategies Electrical Overstress Prevention & Test Best Practices Low Distortion Sine Waveform Generation by an AWG 9:00-10:15 Session 5C: Hybrid Method for Test Data CompressionAn Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-based Scheme Optimizing Test Data Volume Using Hybrid Compression Cost Efficient Methods to Improve Performance of Broadcast Scan 10:45-12:00 Session 6A: Fault DiagnosisHyperactive Faults Dictionary to Increase Diagnosis Throughput Enhancing Transition Fault Model for Delay Defect Diagnosis Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis 10:45-12:00 Session 6B: Special Session: Analog Production Test 2The HiZ problem of Power Management IC testing Total Jitter Measurement for Testing HSIO Integrated SOCs Load-Board/PCB Noise Suppression via Electromagnetic Band Gap Power Plane Patterning 10:45-12:00 Session 6C: Defect Based TestingDefect Detection Rate through IDDQ for Production Testing Variation Aware Analysis of Bridging Fault Testing Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects 13:30-14:45 Session 7A: Panel: How to Increase the Effectiveness of Yield Diagnostics – Is DFM the Answer to This?Organizer/Moderator: Panelists: 13:30-14:45 Session 7B: Power Aware Test GenerationTargeting Leakage Constraints during ATPG Power Management for Wafer-Level Test During Burn-In Test Generation for State Retention Logic 13:30-14:45 Session 7C: Design for Efficient TestArea and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques On-Chip Test Generation Mechanism for Scan-Based Two Pattern Tests Level-Testability of Multi-Operand Adders 15:15-17:00 Session 8A: Industry SessionSystem Level LBIST Implementation CooLBIST : An Effective Approach of Test Power Reduction for LBIST Practical Challenges in Logic BIST Implementation - Case Studies USB2.0 Logic Built In Self Test Methodology Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes Experimental Results of Built-In JItter Measurement for Gigahertz Clock Leading Edge Technology and Test Noise DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug Method Detectability of the Two-dimensional Detector for Time Resolved Emission Measurement Protocol Aware Test Methodologies Using Today's ATE 15:15-16:55 Session 8B: SoC TestCore-Level Compression Technique Selection and SOC Test Architecture Design Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip A Design-for-Debug (DfD) for NoC-based SoC Debugging via NoC Accelerated Functional Testing of Digital Microfluidic Biochips 15:15-16:55 Session 8C: Design Verification and ValidationOn Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation A Robust Automated Scan Pattern Mismatch Debugger An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-level Designs Coverage Directed Test Generation: Godson Experience Nov 27th, 20089:00-10:15 Session 9A: Power Aware Scan TestTest Power Reduction by Blocking Scan Cell Outputs Two-Gear Low-Power Scan Test DCScan: A Power-Aware Scan Testing Architecture 9:00-10:15 Session 9B: Memory Self TestLayout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips A Software-Based Test Methodology for Direct-Mapped Data Cache 9:00-10:15 Session 9C: On-Line TestTime-Multiplexed Online Checking: A Feasibility Study On-Line Instruction-checking in Pipelined Microprocessors Design of FSM with Concurrent Error Detection Based on Viterbi Decoding 10:45-12:00 Session 10A: Power Aware Delay TestingPHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing Power Analysis and Reduction Techniques for Transition Fault Testing 10:45-12:00 Session 10B: Advanced Memory TestInfluence of Parasitic Capacitance Variations on 65nm and 32nm Predictive Model Technology SRAM Core-Cells Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault GDDR5 Training – Challenges and Solutions for ATE-based Test 10:45-12:00 Session 10C: Fault Tolerance and Dependable SystemA Re-design Technique of Datapath Modules in Error Tolerant Applications Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance Analyses on Trend of Accidents in Financial Information Systems Reported by Newspapers from the Viewpoint of Dependability |
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| More Information | |
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General Information
Program Information
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| Committees | |
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Organizing Committee General Co-Chairs Program Chair Program Vice-Chair Finance Chair Local Arrangement Chair Local Arrangement Vice-Chair Registration Chair Publicity Chair Publications Chair Industry Chair Tutorial Chair Audio Visual Chair Secretary North American Liaison European Liaison Ex Officio Program Committee Erika Cota, Brazil |
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