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* The materials on this webpage are presented to ensure timely dissemination of scholarly and technical works. Copyright holders include the IEEE, IET and ACM. Available for personal, non-commercial purposes only.

** CLICK HERE FOR MY DYNAMIC LIST OF PUBLICATIONS FROM THE UNIVERSITY REPOSITORY


 

Books

  1. Xuan-Tu Tran (editor). Emerging Aspects in Electronics and Communication Engineering. Vietnam National University Publisher - Hanoi, 2013, ISBN: 978-604-62-0984-3.

 

Journal Papers

  1. Duy Hieu Bui and Diego Puschini and Simone Bacles-Min and Edith Beigne and Xuan Tu Tran (2017) AES datapath optimization strategies for low-power low-energy multi-security-level Internet-of-Thing applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, ISSN: 1063-8210 (SCI).
  2. Duy-Hieu Bui, Diego Puschini, Simone Bacles-min, Edith Beigne, Xuan-Tu Tran. AES datapath optimization strategies for low-power low-energy multi-security-level Internet-of-Thing Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, ISSN 1063-8210. (SCI)
  3. Xuan-Tu Tran, Tung Nguyen, Hai-Phong Phan, Duy-Hieu Bui. ​AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.8, pp. 1650-1660, Aug. 2017, ISSN: 1745-1337. [DOI] (SCIE)
  4. Hung K. Nguyen, Xuan-Tu Tran. An Efficient Implementation of Advanced Encryption Standard on the Coarse-grained Reconfigurable Architecture. VNU Journal of Computer Science and Communication Engineering (JCSCE), Vol. 32, No. 2, 2016, ISSN: 0866-8612.
  5. Hai-Phong Phan, Xuan-Tu Tran. Design and Modeling of a Voltage-Frequency Controller for Network-on-Chip Routers base on Fuzzy-Logic. VNU Journal of Computer Science and Communication Engineering (JCSCE), pp. 56-65, Vol. 31, No. 2, 2015, ISSN: 0866-8612. [PDF|PrePrint|URL]
  6. Thanh-Vu Le-Van, Xuan-Tu Tran. High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router. REV Journal on Electronics and Communications (JEC), pp. 68-74, Vol. 4, No. 3-4, July-December, 2014, ISSN: 1859 – 387X. [PDF|PrePrint|URL]
  7. Ngoc-Mai Nguyen, Edith Beigne, Duy-Hieu Bui, Nam-Khanh Dang, Suzanne Lesecq, Pascal Vivet, Xuan-Tu Tran. An Overview of H.264 Hardware Encoder Architectures including Low-Power Features. REV Journal on Electronics and Communications (JEC), pp. 8-17, Vol. 4, No. 1-2, January - June, 2014, ISSN: 1859-387X. [PDF|PrePrint|URL]
  8. Xuan-Tu Tran, Van-Huan Tran. An Efficient Architecture of Forward Transforms and Quantization for H.264/AVC Codecs. REV Journal on Electronics and Communications (JEC), pp. 122-129, Vol. 1, No. 2, April-August, 2011, ISSN: 1859-387X. [PDF|PrePrint|URL]
  9. Van-Huan Tran, Xuan-Tu Tran. CoMoSy: a Flexible System-on-Chip Platform for Embedded Applications. Journal of Research, Development, and Application on Information and Communication Theory, pp. 2-11, Vol. E-1, No.4 (8), June 2011, ISSN 1859-3534. [PDF|PrePrint|URL].

Conference Papers in reverse chronologic order

  1. Quang-Linh Nguyen, Dinh-Lam Tran, Duy-Hieu Bui, Duc-Tho Mai, Xuan-Tu Tran. Efficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin Processing. In Proceedings of the 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), pp. 82-87, Hanoi, Vietnam, 5-6 October 2017, ISBN: 978-1-5386-3377-9.
  2. Van-Nam Dinh, Hung K. Nguyen, Xuan-Tu Tran. An IDPSO Algorithm-based Application Mapping Method for Network-on-Chips. In Proceedings of the 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), pp. 104-110, Hanoi, Vietnam, 5-6 October 2017, ISBN: 978-1-5386-3377-9.
  3. Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda. Power Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-Chip. In Proceedings of the 2017 IEEE International Conference on Integrated Circuit Design and Technology, 23-25 May 2017, Texas, USA. [PDF|PrePrint|URL]
  4. Hung K. Nguyen, Xuan-Tu Tran. Design and Implementation of a Hybrid Switching Router for the Reconfigurable Network-on-Chip. In Proceedings of the 2016 International Conference on Advanced Technologies for Communications, 12-14 October 2016, Hanoi, Vietnam.
  5. Hai-Phong Phan, Xuan-Tu Tran. Fuzzy-Logic based Low Power Solution for Network-on-Chip Architectures. In Proceedings of the 2016 International Conference on Advanced Technologies for Communications, 12-14 October 2016, Hanoi, Vietnam.
  6. Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigne, Xuan-Tu Tran. Ultra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT Applications. In Proceedings of the 2016 IEEE International Conference on Integrated Circuit Design and Technology, 27-29 June 2016, Ho Chi Minh city, Vietnam. [PDF|PrePrint|URL]
  7. Thi-Thuy Nguyen, Thanh-Vu Le-Van, Kiem Hung Nguyen, Xuan-Tu Tran. Routing-path Tracking and Updating Mechanism in Reconfigurable Network-on-Chips. In Proceedings of the 2016 IEEE International Conference on Integrated Circuit Design and Technology, 27-29 June 2016, Ho Chi Minh city, Vietnam. [PDF|PrePrint|URL]
  8. Nam-Khanh Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran. Soft-Error Resilient 3D Network-on-Chip Router. The IEEE 7th International Conference on Awareness Science and Technology (IEEE iCAST 2015), 22-24 September 2015, Qinhuangdao, China. [PDF|PrePrint|URL]
  9. Hai-Phong Phan, Xuan-Tu Tran. A Fuzzy-Logic based Voltage-Frequency Controller for Network-on-Chip Routers. In Proceedings of the 11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), Glasgow, Scotland, 29 June - 2 July, 2015. [PDF|PrePrint|URL]
  10. Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran. Reducing Temporal Redundancy in MJPEG using Zipfian Estimation Techniques. In Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2014), pp. 65-68, Okinawa, Japan, November 2014, ISBN: 978-1-4799-5230-4. (Outstanding Student Paper Award & Travel Support Grant Award). [PDF|PrePrint|URL]
  11. Ngoc-Mai Nguyen, Edith Beigne, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran. H.264/AVC Hardware Encoders and Low-Power Features. In Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2014), pp. 77-80, Okinawa, Japan, November 2014, ISBN: 978-1-4799-5230-4. [PDF|PrePrint|URL]
  12. Tien-Luan Vu, Van-Quy Quach, Duy-Hieu Bui, Xuan-Tu Tran. A Low-Cost Implementation of Advance Encryption Standard. In Proceedings of the 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), pp. 50-55, Hanoi, November 2014, ISBN: 978-4-88552-294-9. [PDF|PrePrint|URL]
  13. Hung K. Nguyen, Quang-Vinh Tran, Xuan-Tu Tran. Data Locality Exploitation for Coarse-grained Reconfigurable Architecture in Reconfigurable Network-on-Chips. In Proceedings of the 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), pp. 75-81, Hanoi, November 2014, ISBN: 978-4-88552-294-9.[PDF|PrePrint|URL]
  14. Ngoc-Mai Nguyen, Warody Lombardi, Edith Beigné, Suzanne Lesecq, Xuan-Tu Tran. FIFO-level-based Power Management and its Application to a H.264 encoder. In Proceedings of the 40th Annual Conference of IEEE Industrial Electronics Society (IECON 2014), Dallas, TX, USA, October 28 – November 1, 2014. [PDF|PrePrint|URL]
  15. Thi-Thuy Nguyen, Xuan-Tu Tran. A Novel Asynchronous First-In-First-Out Adapting to Multi-synchronous Network-on-Chips. In Proceedings of the 7th International Conference on Advanced Technologies for Communications (ATC 2014), pp. 365-370, Hanoi, Vietnam. ISBN: 978-1-4799-6955-5. [PDF|PrePrint|URL]
  16. Hai-Phong Phan, Xuan-Tu Tran. Thiết kế và mô hình hoá bộ xử lý lô-gic mờ trong điều khiển tần số - điện áp. 2014 National Conference on Electronics, Communications and Information Technology (REV-ECIT2014), Nha Trang, 18-19/9/2014. (in Vietnamese)
  17. Duy-Hieu Bui, Nam-Khanh Dang, Ngoc-Mai Nguyen, Kim-Hung Nguyen, Xuan-Tu Tran. Xây dựng hệ thống mô phỏng và kiểm chứng cho bộ mã hoá tín hiệu video H.264/AVC. 2014 National Conference on Electronics, Communications and Information Technology (REV-ECIT2014), Nha Trang, 18-19/9/2014. (in Vietnamese)
  18. Nam-Khanh Dang, Xuan-Tu Tran, Alain Merigot. An Efficient Hardware Architecture for Inter-Prediction in H.264/AVC Encoders. In Proceedings of the 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS 2014), pp. 294-297, April 23-25, 2014, Warsaw, Poland, ISBN: 978-1-4799-4558-0. [PDF|PrePrint|URL]
  19. Thanh-Vu Le-Van, Hai-Phong Phan, Xuan-Tu Tran. High-Level Modeling of a Novel Reconfigurable Network-on-Chip Router. In Proceedings of the first NAFOSTED Conference on Information and Computer Science (NICS 2014), Hanoi, 13-14 March 2014, ISBN: 978-604-67-0228-3. [PDF|URL]
  20. Hai-Phong Phan, Hung K. Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran. System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder. In Proceedings of the 2013 National Conference on Electronics and Communications (REV2013-KC01), Hanoi, December 2013, ISBN: 978-6-04934-664-4. [PDF|URL]
  21. Nam-Khanh Dang, Van-Mien Nguyen, Xuan-Tu Tran. A VLSI Implementation for Inter-Prediction Module in H.264/AVC Encoders. In Proceedings of the 2013 IEICE International Conference on Integrated Circuits, Devices, and Verification (ICDV 2013), pp. 73-78, Ho Chi Minh city, Vietnam, November 2013, ISBN: 978-4-88552-282-6. [PDF|URL]
  22. Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran. An Efficient Video Coding Algorithm Targeting Low Bitrate Stationary Cameras. In Proceedings of the 2013 IEICE International Conference on Integrated Circuits, Devices, and Verification (ICDV 2013), pp. 127-132, Ho Chi Minh city, Vietnam, November 2013, ISBN: 978-4-88552-282-6. [PDF]
  23. Ngoc-Mai Nguyen, Edith Beigne, Suzanne Lesecq, Pascal Vivet, Duy-Hieu Bui, Xuan-Tu Tran. Hardware Implementation for Entropy Coding and Byte Stream Packing Engine in H.264/AVC. In Proceedings of the 2013 International Conference on Advanced Technologies for Communications (ATC 2013), pp. 360-365, October 2013, Ho Chi Minh city, Vietnam, ISBN: 978-1-4799-1086-1. [PDF|PrePrint|URL]
  24. Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran. High-Performance Adaption of ARM Processor into Network-on-Chip Architectures. In Proceedings of the 26th IEEE System-on-Chip Conference (IEEE SOCC 2013), pp. 222-227, September 2013, Erlangen, Germany. [URL|DOI]
  25. Thi-Thuy Nguyen, Xuan-Tu Tran. A Synchronous-to-Synchronous FIFO Architecture for Multi-synchronous Network-on-Chips. International Conference on Green and Human Information Technology (ICGHIT 2013), pp. 111-117, Hanoi, Vietnam, February 27 – March 1, 2013.
  26. Viet-Thang Nguyen, Xuan-Tu Tran, Ha Vu Le . An Efficient Algorithm of Inter-Prediction Coding for H.264/AVC Encoders. International Conference on Green and Human Information Technology (ICGHIT 2013), Hanoi, Vietnam, February 27 – March 1, 2013.
  27. Tran Van Hoang, Nguyen Ly Thien Truong, Hoang Trang, Xuan-Tu Tran. Design and Implementation of a SoPC System for Speech Recognition. International Conference on Green and Human Information Technology (ICGHIT 2013), Hanoi, Vietnam, February 27 – March 1, 2013, ISSN: 1876-1100 (Scopus Journal).
  28. Ngoc-Mai Nguyen, Xuan-Tu Tran, Pascal Vivet, Suzanne Lesecq. An Efficient Context Adaptive Variable Length Coding Architecture for H.264/AVC Video Encoders. In Proceedings of the 5th International Conference on Advanced Technologies for Communications (ATC 2012), pp. 158-164, Hanoi, October 2012, ISBN: 978-1-4673-4350-3. [PDF|PrePrint|URL] (Best Student Paper Award)
  29. Thanh-Vu Le-Van, Xuan-Tu Tran. Simulation and Performance Evaluation of a Network-on-Chip Architecture based on SystemC. In Proceedings of the 5th International Conference on Advanced Technologies for Communications (ATC 2012), pp. 170-175, Hanoi, October 2012, ISBN: 978-1-4673-4350-3.
  30. Thanh-Vu Le-Van, Dien-Tap Ngo, Xuan-Tu Tran. A SystemC based Simulation Platform for Network-on-Chip Architectures. In Proceedings of the 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), pp. 132-136, Danang, August 2012, ISBN: 978-4-88552-264-2.
  31. Duy-Hieu Bui, Van-Huan Tran, Van-Mien Nguyen, Duc-Hoang Ngo, Xuan-Tu Tran. A Hardware Architecture for Intra Prediction in H.264/AVC Encoder. In Proceedings of the 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), pp. 95-100, Danang, August 2012, ISBN: 978-4-88552-264-2.
  32. Nam-Khanh Dang, Thanh-Vu Le-Van, Xuan-Tu Tran. FPGA Implementation of a Low Latency and High Throughput Network-on-Chip Router Architecture. In Proceedings of the 2011 International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2011), Hanoi, August 2011.
  33. Duy-Hieu Bui, Xuan-Tu Tran. Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder. In Proceedings of the 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), Hanoi, August 2011.
  34. Xuan-Tu Tran, Van-Huan Tran. Cost-Efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC Encoders. In Proceedings of the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (IEEE DDECS 2011), pp. 47-52, Cottbus, Germany, April 2011.
  35. Van-Huan Tran, Xuan-Tu Tran. An Efficient Architecture Design for VGA Monitor Controller. In Proceedings of the International Conference on Consumer Electronics, Communications and Networks (IEEE CECNet 2011), pp. 3917-3921, Hubei, China, April 2011, ISBN: 978-1-61284-459-6.
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